Impact of pulse quenching effect on soft error vulnerabilities in combinational circuits based on standard cells
نویسندگان
چکیده
In this study, we investigated the impact of pulse quenching effect on the soft error vulnerabilities in combinational circuits. Simulation results illustrate that soft error vulnerabilities could be reduced by 4–16% for the benchmark circuits when the pulse quenching effect is introduced. By adjusting the cell orientations of the quenching cells in the layout, the soft error vulnerabilities could be further reduced. It is suggested that new placement algorithm considering circuit reliability should be designed to reduce the circuit soft error vulnerabilities. & 2012 Elsevier Ltd. All rights reserved.
منابع مشابه
Symbolic Simulation of the Propagation and Filtering of Transient Faulty Pulses
This paper is concerned with statically analyzing the susceptibility of arbitrary combinational circuits to single event upsets that are becoming a significant concern for reliability of commercial electronics. For the first time, a fast and accurate technique based on static, vector-less analysis of soft error rates (SER) in general combinational circuits is proposed. The analysis technique is...
متن کاملAn Accurate and Efficient Model of Electrical Masking Effect for Soft Errors in Combinational Logic
Accurate modeling of the electrical masking effect of soft errors for combinational logic circuits represents a significant challenge in soft error rate analysis. Previous proposed models for electrical masking effect can introduce large estimation error. In this work, we use table lookup MOSFET models to accurately capture the nonlinear properties of submicron MOS transistors. Based on these m...
متن کاملSoft error estimation and mitigation of digital circuits by characterizing input patterns of logic gates
Soft errors caused by particles strike in combinational parts of digital circuits are a major concern in the design of reliable circuits. Several techniques have been presented to protect combinational logic and reduce the overall circuit Soft Error Rate (SER). Such techniques, however, typically come at the cost of significant area and performance overheads. This paper presents a low area and ...
متن کاملThe Effect of Pipeline Depth on Logic Soft Errors
Soft errors arising from particle strikes to combinational logic circuits can be masked logically (by dominant inputs), electrically (the pulse is too weak to flip a node), or by opportune timing (the transient pulse arrives at a downstream latch when the latch is opaque). The latter effect—timing-window masking—is commonly approximated analytically by computing the ratio of the length of the l...
متن کاملModeling the Impact of Device and Pipeline Scaling on the Soft Error Rate of Processor Elements
This paper examines the effect of technology scaling and microarchitectural trends on the rate of soft errors in CMOS memory and logic circuits. We describe and validate an end-to-end model that enables us to compute the soft error rates (SER) for existing and future microprocessor-style designs. The model captures the effects of two important masking phenomena, electrical masking and latching-...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید
ثبت ناماگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید
ورودعنوان ژورنال:
- Microelectronics Journal
دوره 44 شماره
صفحات -
تاریخ انتشار 2013